1. Field of the Invention
This invention relates to a structure of semiconductor device package, and more particularly to a structure of semiconductor device package with multi-chips and method of the same, the structure can reduce the package size and improve the yield and reliability.
2. Description of the Prior Art
In recent years, the high-technology electronics manufacturing industries launch more feature-packed and humanized electronic products. Rapid development of semiconductor technology has led to rapid progress of a reduction in size of semiconductor packages, the adoption of multi-pin, the adoption of fine pitch, the minimization of electronic components and the like. The purposes and the advantages of wafer level package includes decreasing the production cost, decreasing the effect caused by the parasitic capacitance and parasitic inductance by using the shorter conductive line path, acquiring better SNR (i.e. signal to noise ratio).
Because conventional package technologies have to divide a dice on a wafer into respective dies and then package the die respectively, therefore, these techniques are time consuming for manufacturing process. Since the chip package technique is highly influenced by the development of integrated circuits, therefore, as the size of electronics has become demanding, so does the package technique. For the reasons mentioned above, the trend of package technique is toward ball grid array (BGA), flip chip ball grid array (FC-BGA), chip scale package (CSP), Wafer level package (WLP) today. “Wafer level package” is to be understood as meaning that the entire packaging and all the interconnections on the wafer as well as other processing steps are carried out before the singulation (dicing) into chips (dies). Generally, after completion of all assembling processes or packaging processes, individual semiconductor packages are separated from a wafer having a plurality of semiconductor dies. The wafer level package has extremely small dimensions combined with extremely good electrical properties.
In the manufacturing method, wafer level chip scale package (WLCSP) is an advanced packaging technology, by which the die are manufactured and tested on the wafer, and then singulated by dicing for assembly in a surface-mount line. Because the wafer level package technique utilizes the whole wafer as one object, not utilizing a single chip or die, therefore, before performing a scribing process, packaging and testing has been accomplished; furthermore, WLP is such an advanced technique so that the process of wire bonding, die mount and under-fill can be omitted. By utilizing WLP technique, the cost and manufacturing time can be reduced, and the resulting structure of WLP can be equal to the die; therefore, this technique can meet the demands of miniaturization of electronic devices. Further, WLCSP has an advantage of being able to print the redistribution circuit directly on the die by using the peripheral area of the die as the bonding points. It is achieved by redistributing an area array on the surface of the die, which can fully utilize the entire area of the die. The bonding points are located on the redistribution circuit by forming flip chip bumps so the bottom side of the die connects directly to the printed circuit board (PCB) with micro-spaced bonding points.
Although WLCSP can greatly reduce the signal path distance, it is still very difficult to accommodate all the bonding points on the die surface as the integration of die and internal components gets higher. The pin count on the die increases as integration gets higher so the redistribution of pins in an area array is difficult to achieve. Even if the redistribution of pins is successful, the distance between pins will be too small to meet the pitch of a printed circuit board (PCB). That is to say, such process and structure of prior art will suffer yield and reliability issues owing to the huge size of package. The further disadvantage of former method are higher costs and time-consuming for manufacture.
WLP technique is an advanced packaging technology, by which the die are manufactured and tested on the wafer, and then the wafer is singulated by dicing for assembly in a surface-mount line. Because the wafer level package technique utilizes the whole wafer as one object, not utilizing a single chip or die, therefore, before performing a scribing process, packaging and testing has been accomplished; furthermore, WLP is such an advanced technique so that the process of wire bonding, die mount and under-fill can be omitted. By utilizing WLP technique, the cost and manufacturing time can be reduced, and the resulting structure of WLP can be equal to the die; therefore, this technique can meet the demands of miniaturization of electronic devices.
Though the advantages of WLP technique mentioned above, some issues still exist influencing the acceptance of WLP technique. For instance, the coefficient of thermal expansion (CTE) difference (mismatching) between the materials of a structure of WLP and the mother board (PCB) becomes another critical factor to mechanical instability of the structure. A package scheme disclosed by U.S. Pat. No. 6,271,469 suffers the CTE mismatching issue. It is because the prior art uses silicon die encapsulated by molding compound. As known, the CTE of silicon material is 2.3, but the CTE of molding compound is around 20-80. The arrangement causes chip location be shifted during process due to the curing temperature of compound and dielectric layers materials are higher and the inter-connecting pads will be shifted that will causes yield and performance problem. It is difficult to return the original location during temperature cycling (it caused by the epoxy resin property if the curing Temp near/over the Tg). It means that the prior structure package can not be processed by large size, and it causes higher manufacturing cost.
Further, some technical involves the usage of die that directly formed on the upper surface of the substrate. As known, the pads of the semiconductor die will be redistributed through redistribution processes involving a redistribution layer (RDL) into a plurality of metal pads in an area array type. The build up layer will increase the size of the package. Therefore, the thickness of the package is increased. This may conflict with the demand of reducing the size of a chip.
Moreover, the prior art suffers complicated process to form the “Panel” type package. It needs the mold tool for encapsulation and the injection of mold material. It is unlikely to control the surface of die and compound at same level due to warp after heat curing the compound, the CMP process may be needed to polish the uneven surface. The cost is therefore increased.
In view of the aforementioned, the present invention provides a new structure with multi-chips and method for a panel scale package (PSP) to overcome the above drawback.